Exploration on Routing Configuration of HNoC with Intelligent On-Chip Resource Management

Abstract

The Heterogeneous Network-on-Chip (HNoC) integrates CPU cores, Graphic Processing Unit (GPU) cores, last-level-cache and memory controllers. The heterogeneity of this architecture inevitably brings resource contention and energy shortage. In this work, we first study the impact of different capacity of router buffers on communication delay and energy consumption. After comprehensive evaluation with a spectrum of benchmarks with different characteristics, we reveal the implicit tradeoff between performance and energy consumption under different constrains of buffer resource. We further show that intelligently allocating more on-chip network buffer resources to compute-intensive nodes can significantly improve system performance. We introduce a runtime strategy that dynamically allocates network buffers to applications based on application characteristics. Our evaluation shows that our system reduces the communication delay by 55.47% on average, and reduces energy consumption of the system by 21% on average.