Design of a Hippocampal Cognitive Prosthesis Chip

Abstract

SUMMARY This paper presents a hippocampal cognitive prosthesis chip designed for restoring the ability to form new long-term memories due to hippocampal system damage. The system-on-chip (SOC) consists of a 16-channel micro-power low-noise amplifier (LNA), high-pass filters, analog-digital converters (ADCs), a 16-channel spike-sorter, a generalized Laguerre-Volterra model multi-input, multi-output (GLVM-MIMO) hippocampal processor, an 8-channel neural stimulator and peripheral circuits. The proposed LNA achieved a voltage gain of 50 dB, input-referred noise of 3.95 μVrms, and noise efficiency factor (NEF) of 3.45 with the power consumption of 3.3 μW. High-pass filters with a 300-Hz bandwidth are used to filter out the unwanted local field potential (LFP). 4 12-bit successive approximation register (SAR) ADCs with a signal-to-noise-and-distortion ratio (SNDR) of 63.37 dB are designed for the digitization of the neural signals. A 16-channel spike-sorter has been integrated in the chip enabling a detection accuracy of 98.3% and a classification accuracy of 93.4% with power consumption of 19 μW/ch. The MIMO hippocampal model processor predict output spatio-temporal patterns in CA1 according to the recorded input spatio-temporal patterns in CA3. The neural stimulator performs bipolar, symmetrical charge-balanced stimulation with a maximum current of 310 μA, triggered by the processor output. The chip has been fabricated in 40 nm standard CMOS technology, occupying a silicon area of 3 mm2