Performance improvement of DVFS based 16 bit SAR ADC

Abstract

Analog-to-digital converters (ADCs) at elevated efficiency are vital components for elevated quality image sensors growth. In order to achieve the necessary resolution at a specific velocity, these systems need a large amount of ADCs. In addition, energy dissipation has now become a main output for analog models, especially for mobile equipment. Such a circuit design is a difficult job, requiring a mixture of sophisticated digital circuit design, analog expertise and iterative design. The sharing of amplifiers was frequently employed for reducing dissipation of energy in ADC pipelines. In this paper we present the topology of a 16-bit ADC pipeline, developed in 45 nm CMOS. Its efficiency is likened to a standard Scaling configuration for amplifier and a completely shared amplifier.