Utilization of unsigned inputs for NAND flash-based parallel and high-density synaptic architecture in binary neural networks

Abstract

A novel design method using unsigned input is proposed for a high-density and parallel synaptic string architecture capable of bit-wise operation and bit-counting utilizing NAND flash memory. Though the NAND flash memory has a cell string structure, unsigned binary input enables analogue and parallel bit-counting in NAND flash memory, while achieving high accuracy comparable to that of signed input. Adopting unsigned input allows using current sense amplifier as neuron circuit, which reduces burden of peripheral circuits. In addition, the operation scheme for convolution layers is proposed for parallel convolution operation utilizing NAND flash memory. We show that sufficiently low device variation of 7.2 % obtained by applying 1 erase or program pulse achieves accuracy of 98.12 % and 87.12 % for MNIST and CIFAR 10 patterns, respectively.