Modeling and Simulation-Based Investigation of 2-D Symmetric Double Gate Dopingless-TFET and Its Circuit Performance for Low-Power Applications

Abstract

Dopingless tunnel field effect transistor (DL-TFET) exhibits a great potential for lowering the sub-threshold current and hence increases the ION/IOFF ratio because of its electrostatically doped source and drain. An analytical model for double gate dopingless tunnel field transistor (DG-DL TFET) is developed, for the first time, by calculating the source and drain work-function-induced doping and using it for solving the 2D Poisson’s equation in various regions. Electric potentials, energy band diagrams, electric field, corresponding drain current characteristics, and trans-conductance are obtained through the developed model and are validated by performing extensive device simulation for different gate and drain bias voltages. An excellent match between modeled and simulated results proves the efficacy of the developed model. The ION current obtained in Si-based dopingless TFET is 0.16 µA/µm, IOFF has reduced to 0.296 fA/µm and ION/IOFF obtained from the proposed device structure is 5.4 × 108, and the sub-threshold swing is 50.77 mV/decade. The DG-DL TFET is analyzed for resistive load inverter characteristics and has been further investigated for realizing digital logic functions by controlling the gates of the device independently. The realization of NAND gate requires one “p-type DG-DL TFET”, whereas OR gate requires one “n-type DG-DL TFET”. The implementations of single bias-controlled logics are useful as they render energy-efficient operations and simultaneously increase the packaging density.