A comprehensive investigation of silicon film thickness (TSI) of nanoscale DG TFET for low power applications

Abstract

In this work we demonstrate an N-channel tunnel field effect transistor (TFET) i.e. double gate N-TFET for improved subthreshold slope (SS) and OFF-state leakage current (IOFF) with reference to drain bias (VDS), and body thickness (TSI). Device thickness is becoming a crucial parameter as more devices can built on thin film and integrate double or multi-gate MOSFETs. In this model we analyze the impact of VDS and TSI on the device performances and express the limitation of TTS with respect to ON-state current (ION), electric field, energy band diagram, etc. TFETs have become popular because these devices can operate in the sub-threshold region with the larger transconductance to current ratio (gm/Id) than MOSFETs, the current turn-on mechanism being interband tunneling rather than thermionic emission. The proposed model can achieve a subthreshold swing less than 35 mV/decade that is desirable for designing low-power high-frequency analog integrated digital circuit applications.