Discrete-Time Domain Current Control Strategy for High Power Grid-Connected Converters

Abstract

For high-power grid-connected converters, the switching frequency usually is low. Consequently, the adverse effects enforced by the control delay and discretizing errors are heavy. However, traditional current control strategies generally ignore these effects, reducing the performance of the designed controller. Recently, some strategies were presented to compensate for the control delay and the discretizing errors. However, most suffer from low dynamic response and high sensitivity to the power grid harmonics. Therefore, a current control strategy combining the bridge arm-side and the grid-side currents is designed directly in the discrete-time domain, and pole-zero placement is used in synchronous coordinates. Meanwhile, a differentiator to the capacitor voltage is introduced to estimate the grid-side currents. Consequently, hardware complexity and the corresponding control cost are reduced. The discrete-time model of the converter with LCL is built in synchronous coordinates as the output filter, including the computational delay, firstly. The corresponding structure of the combined state-space control scheme is as follows: the harmonic control loop of the grid-side currents is constructed and combined with the fundamental current control loop on the bridge arm-side using the full state-feedback control. And then, the integral controller is introduced for improved disturbance rejection, and the reference-feedforward controller is designed to increase the reference-tracking dynamic performance. Consequently, the closed-loop transfer function of the system is obtained based on the discrete-time model and the control scheme. Then the state feedback function matrix and the feedforward module are optimized based on the pole-zero placement. Finally, a differentiator is introduced to estimate the grid-side currents, reducing the hardware cost. Experiment results based on a hardware-in-loop simulator show that the response time of the bridge arm-side currents to a 1 000 A step-up change is about 4.5 ms; the recovery time of the bridge arm-side currents facing a grid-voltage dip of 0.4(pu) is about 10ms; and the total harmonic distortion of the grid-side currents is 2.28%, below the 5% limit given in standards, in the circumstances of 6% fifth and seventh harmonic components appearing in the grid voltage. Finally, to verify the robustness of the proposed strategy to the parameter deviations, the actual system parameters are deviated artificially from their nominal values. The results show that the proposed strategy can operate satisfactorily in the range of ±40% parameter deviations, and the influence of the parameter deviations is low. The following conclusions can be drawn from the experiment results: (1) Compared with the typical discrete-time state-space control strategy, the proposed strategy keeps the same dynamic performance while improving the capability of rejecting the grid harmonic disturbance. (2) The proposed control strategy simplifies the design complexity based on the direct pole-zero placement and increases freedom degrees by combining the design of fundamental current and harmonic control loops. (3) The differentiator to the capacitor voltage is designed to acquire grid-side currents without additional current sensors and the corresponding sampling circuit, reducing the hardware complexity and the cost.