Low Power Analog and Digital (7,5) Convolutional Decoders in 65 nm CMOS

Abstract

Targeting emerging energy constrained bio-implantable or wearable wireless devices, this work presents design space exploration of decoding circuits for $(7,5)8 convolutional codes in 65 nm CMOS for ultra-low power operation. Decoders operating in digital and analog domains are designed and measured for energy efficiency, bit error rate (BER) performance and throughput. For the analog decoders which are sensitive to noise and device mismatch, the overall effects of transistor dimensions on the output BER are also investigated. The digital implementation with 0.11 ${\rm mm}2 area consumes minimum energy at 0.32 V supply, which gives 9 pJ/b energy efficiency at 125 kb/s and 2.9 dB coding gain. Likewise, in analog domain, three decoding circuits are fabricated that share the same topology and design, except for transistor dimensions. The largest analog decoding core (AD1) takes 0.104 ${\rm mm}2 and the other two (AD2 and AD3) are 0.035 ${\rm mm}2 and 0.015 ${\rm mm}2, respectively. Consequently, coding gain in trade-off with silicon area and throughput is presented. The analog decoders operate with 0.8 V supply, and 2.3 dB coding gain with 10 pico-Joules per bit (pJ/b) energy efficiency is achieved at 2 Mbps.