A Novel 8T SRAM Cell with Improved Read and Write Margins

Abstract

A highly stable 8T SRAM cell is presented to improve the Static Noise Margin (SNM). The proposed 8T SRAM cell uses a single-bit line structure to perform read and write operation. The design enhances the write ability by breaking-up the feedback loop of the inverter pair. It also improves the read stability by eliminating the effects from the bit-line. The simulations show that the proposed 8T cell offers 2.07x read static noise margin, 1.41x and 2.60x in write `0' margin compared to the conventional 6T cell and 7T cell, respectively. Besides, the proposed structure has a significant improvement in writing `1' operation and HSNM.