Power optimization in 10t full adder for 4 bit array multiplier

Abstract

A 10T full adder is a low power consumption circuit. It is an eminent circuit with minimum transistor count. The modified CMOS 10T full adder is designed based on low power delay product and it is implemented in array multiplier. Array Multiplier is a circuit used to multiply two four bit binary numbers. When a multiplicand is multiplied by an array multiplier it generates a partial product and they are shifted according to their bits and then added. It reduces the number of partial products generated while multiplying the values. The modified CMOS 10T full adder circuit increases the performance of the multiplier. To analyze the performance of modified adder, CMOS 10T adder is simulated using tanner EDA tools with 130 nm technology.