A silicon biristor with reduced operating voltage: Proposal and analysis

Abstract

In this paper, using 2-D simulations, we report a silicon biristor with reduced operating voltage using the surface accumulation layer transistor (SALTran) concept. The electrical characteristics of the proposed SALTran biristor are simulated and compared with that of a conventional silicon biristor with identical dimensions. The proposed device is optimized with respect to the device parameters to ensure a reasonable latch window while maintaining low latch voltages. Our results demonstrate that the SALTran biristor exhibits a latch-up voltage of 2.14 V and a latch-down voltage of 1.68 V leading to a 57% lower operating voltage compared to the conventional silicon biristor.