Recently, nonlinear composite correlation filters have been proposed for distortion-invariant pattern recognition. The filter design is based on logical operations and the correlation is computed with a nonlinear operation called morphological correlation. In this paper a new implementation in parallel hardware of these kinds of filters for image recognition is proposed. The architecture is designed for a Field Programmable Gate Array (FPGA) device. The proposed design performs the most time consuming task of the recognition procedure. In consequence, it reduces the time required for the nonlinear operations in the spatial domain. Simulation results are provided and discussed. © 2013 Springer Science+Business Media Dordrecht.
CITATION STYLE
Martinez-Diaz, S. (2013). A hardware design for binary image recognition. In Lecture Notes in Electrical Engineering (Vol. 229 LNEE, pp. 491–499). Springer Verlag. https://doi.org/10.1007/978-94-007-6190-2_37
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