FPGA implementation of radix-2 based FFT architecture for real-valued signal processing

Abstract

This paper investigates the various pipelined FFT architectures based on radix-2, radix-22 & radix-23 algorithms. The implemented FFTs are designed by employing techniques such as folded transform and register minimization. It maximizes the utilization of hardware resource and reduces the number of adders. It requires less area and achieves high throughput and low latency. For higher values of N, the FFT (Fast Fourier Transform) architecture has many butterfly structures which has been optimized. The FFT outputs are usually obtained in a bit reversed order and a new approach for reordering the bit-reversed orders has been proposed.