Asymmetric multilevel inverter topology and its fault management strategy for high‐reliability applications

Abstract

As the applications of power electronic converters increase across multiple domains, so do the associated challenges. With multilevel inverters (MLIs) being one of the key technologies used in renewable systems and electrification, their reliability and fault ride‐through capabilities are highly desirable. While using a large number of semiconductor components that are the leading cause of failures in power electronics systems, fault tolerance against switch open‐circuit faults is necessary, especially in remote applications with substantial maintenance penalties or safety‐critical operation. In this paper, a fault‐tolerant asymmetric reduced device count multilevel inverter topology producing an 11‐level output under healthy conditions and capable of operating after open-circuit fault in any switch is presented. Nearest‐level control (NLC) based Pulse width modulation is implemented and is updated post‐fault to continue operation at an acceptable power quality. Reliability analysis of the structure is carried out to assess the benefits of fault tolerance. The topology is compared with various fault‐tolerant topologies discussed in the recent literature. Moreover, an artificial intelligence (AI)‐based fault detection method is proposed as a machine learning classi-fication problem using decision trees. The fault detection method is successful in detecting fault location with low computational requirements and desirable accuracy.