CMOS-compatible wafer-scale Si subulate array for superb switching uniformity of RRAM with localized nanofilaments

Abstract

Resistive switching random access memory (RRAM) is one of the most promising candidates with high-density three-dimensional integration characteristics for next-generation nonvolatile memory technology. However, the poor uniformity issue caused by the stochastic property of the conductive filament (CF) impedes the large-scale manufacture of RRAM chips. Subulate array has been introduced into the RRAM to minimize the CF randomness, but the methods are cumbersome, expensive, or resolution-limited for large-scale preparation. In this work, Si subulate array (SSA) substrates with different curvature radii prepared by a wafer-scale and nanoscale-controllable method are introduced for RRAM fabrication. The SSA structure, which induces a quasi-single CF or a few CFs formed in the tip region (TR) of the device as evidenced by the high-resolution transmission electron microscopy and energy dispersive spectroscopy characterization, dramatically improves the cycle-to-cycle and device-to-device uniformity. Decreasing the curvature radius of the TR significantly improves the device performance, including switching voltages, high/low resistance states, and retention characteristics. The improved uniformity can be attributed to the enhanced local electric field in the TR. The proposed SSA provides a low-cost, uniform, CMOS-compatible, and nanoscale-controllable optimization strategy for the large-scale integration of highly uniform RRAM devices.