Process coordination with fetch-and-increment

Abstract

The fetch-and-add (F&A) operation has been used effectively in a number of process coordination algorithms. In this paper we assess the power of fetch-and-increment (F&I) and fetch-and-decrement (F&D), which we view as restricted forms of F&A in which the only addends permitted are ±1. F&A-based algorithms that use only unit addends are thus trivially expressed with just F&I and F&D. Our primary contributions are new F&I/F&D algorithms for readers/writers coordination and barrier synchronization for dynamically-sized groups. We also restructure an existing F&A-based algorithm for queues-with-multiplicity to obtain an algorithm using just F&I and F&D. When executed on certain hardware architectures, most of these algorithms are free of serial bottlenecks. We also discuss a general technique for implementing F&A using F&I/F&D at a cost logarithmic in the number of processors.