A universal reversible gate architecture for designing n-bit comparator structure in quantum-dot cellular automata

Abstract

Logic computing around quantum-dot cellular automata (QCA) has emerging area of high-speed nanoelectronics. We implemented the synthesis of the reversible comparator circuit in QCA regime that employs minimum primitives results. This paper presents a universal reversible quantum-dot cellular automata gate (URQG) and its implementation in QCA technology. The efficiency of the proposed gate in designing reversible circuits is validated by implementing the QCA standard benchmark Boolean functions. We also synthesize n-bit comparator, where proposed URQG and existing Feynman gates are cascaded together. Finally, in a QCA paradigm, we designed layout for the 1-bit and 2-bit comparators, and prove the better primitives results over existing layouts. Synthesis results indicate that the proposed 1-bit reversible comparator has achieved 75% improvement in delay and 95% improvement in quantum cost compared to existing design. The proposed gate currently aims the testability world such as cell deposition and HDLQ that test suite. The authors also show the energy dissipation results for existing benchmark reversible gates introduced in state-of-art technology and URQG gate that proposed herewith. QCADesigner tool is used to design and verify the functionality of the proposed designs. QCAPro tool is used for energy dissipation analysis of the proposed gate.