An 11T SRAM Cell for the Dual-Direction In-Array Logic/CAM Operations

Abstract

The in-memory computing (IMC) architecture eliminates the frequent data transfers between the memory banks and the processor cores. Researchers have utilized different SRAM cells to implement the in-memory logic operations. However, most of the previous works implement the column-wise logic/CAM operations, which require the column-wise stored operands. These column-wise logic/CAM operations are incompatible with the traditional row-wise SRAM mode. This brief proposes an SRAM cell with 11 transistors, which can work in four operation modes: the SRAM mode, the logic mode, and the BCAM/TCAM modes. All the operations in these four modes can be performed both in the column-wise and the row-wise style. The incompatibility between different modes is eliminated. In the logic mode, the proposed SRAM achieves frequency of 595MHz and energy consumption of 17.94fJ/bit at 1.2V with TSMC 65nm technology file. In the BCAM/TCAM modes, it can work with 407MHz, and it consumes 0.62fJ/bit and 1.38fJ/bit at 1.2V