High speed VLSI Squaring unit of Binary Numbers Design with Yavadunam Sutra and Bit Reduction

Abstract

Vedic Mathematics is an ancient Indian algebra in which 16 sutras are used to measure. For excellent performance, most high-speed applications such as cryptography and digital signal processing need powerful and high-speed multipliers. Squaring is a specific case of multiplication. A specialized squaring device can greatly boost the measurement period and significantly reduce the delay. This study discusses the concept of a new square architecture utilizing Vedic-mathematics sutra "Yavadunam." The proposed method uses the amount deficit from the closest base to calculate every operand's circle. The square of a larger number of magnitude is reduced by this method to a smaller multiplication of magnitude and an addition operation.