Void-free Copper Electrodeposition in High Aspect Ratio, Full Wafer Thickness Through-Silicon Vias with Endpoint Detection

Abstract

High density interconnects are required for increased input/output for microelectronics applications, incentivizing the development of Cu electrochemical deposition (ECD) processes for high aspect ratio through-silicon vias (TSVs). This work outlines Cu ECD processes for 62.5 μ m diameter TSVs, etched into a 625 μ m thick silicon substrate, a 10:1 aspect ratio. Cu ECD in high aspect ratio features relies on a delicate balance of electrolyte composition, solution replenishment, and applied voltage. Implementing a CuSO 4 -H 2 SO 4 electrolyte, which contains suppressor and a low chloride concentration, allows for a tunable relationship between applied voltage and localized deposition in the vias. A stepped potential waveform was applied to move the Cu growth front from the bottom of the via to the top. Sample characterization was performed through mechanical cross-sections and X-ray computed tomography (CT) scans. The CT scans revealed small seam voids in the Cu electrodeposit, and process parameters were tuned accordingly to produce void-free Cu features. During the voltage-controlled experiments, measured current data showed a characteristic current minimum, which was identified as an endpoint detection method for Cu deposition in these vias. We believe this is the first report of this novel endpoint detection method for TSV filling.