Charge Pump and Loop Filter for Low Power PLL Using 130nm CMOS Technology

Abstract

A tri-state charge pump circuit and second order low pass filter circuit were designed to be used in Phase Lock Loop (PLL) system. The proposed design reduces the non-ideal effects such as a current mismatch and charge sharing. Therefore, it can be minimized by providing an equal value for the two switches UP and DOWN. While the charge pump output determines the output condition of the low pass filter. The proposed design have been simulated by using 130nm Complementary Metal Oxide Semiconductor (CMOS) technology in Cadence Tools. The simulation also includes the parameters for tri-state charge pump and second order low pass filter using voltage supply of 1.2 V. The power consumption of the design is 2.07 mW with the output voltage swing from 288 mV to 413.8 mV. The frequency achieved from the proposed design is 4.7 GHz. The total area of the layout that have been measured is 31.4 μm x 22.6 μm (0.7096 mm2). Thus, the proposed design able to achieve the scope of low power consumption and high frequency in smaller technology.