Abstract
We propose a new process technique for fabricating very high-density trench MOSFETs using 3 mask layers with oxide spacers and a self-aligned technique. This technique reduces the device size in trench width, source, and p-body region with a resulting increase in cell density and current driving capability as well as cost-effective production capability. We were able to obtain a higher breakdown voltage with uniform oxide grown along the trench surface. The channel density of the trench DMOSFET with a cell pitch of 2.3-2.4 μm was 100 Mcell/in2 and a specific on-resistance of 0.41 mΩcm2 was obtained under a blocking voltage of 43 V.
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CITATION STYLE
Kim, J., Roh, T. M., Kim, S. G., Park, I. Y., Yang, Y. S., Lee, D. W., … Kang, Y. I. (2002). A novel process for fabricating high density trench MOSFETs for DC-DC converters. ETRI Journal, 24(5), 333–340. https://doi.org/10.4218/etrij.02.0102.0501
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