Design of high-speed H.265 sample adaptive offset estimation for ultra-hd TV encoding using clock synchronization code

Abstract

Sample adaptive offset (SAO) is a recently presented in-circle separating segment in H.265/High Efficiency Video Coding (HEVC). SAO adds to a striking coding effectiveness enhancement; the estimation of SAO parameters commands the multifaceted nature of in-circle sifting in HEVC encoding. Double clock engineering that procedures statistics collection (SC) and parameter decision (PD), the two principle useful squares of SAO estimation, at high-and low-speed timekeepers, separately. Such a technique decreases the general zone by 56% by tending to the heterogeneous information streams of SC and PD. This exploration work endeavors to ad lib the working clock speed by adjusting a double clock synchronizer VLSI structure of H.265 ultra HD encoder and control minimization. To additionally enhance the territory and power productivity, calculation engineering co-improvements are connected, including a coarse range selection (CRS) and an accumulator bit width reduction (ABR). They together may accomplish another 25% territory decrease. The proposed VLSI configuration is fit for handling 8k at 120-outlines/s encoding.