An implementation for a fast public-key cryptosystem

Abstract

In this paper we examine the development of a high-speed implementation of a system to perform exponentiation in fields of the form GF(2n). For sufficiently large n, this device has applications in public-key cryptography. The selection of representation and observations on the structure of multiplication have led to the development of an architecture which is of low complexity and high speed. A VLSI implementation has being fabricated with measured throughput for exponentiation for cryptographic purposes of approximately 300 kilobits per second. © 1991 International Association for Cryptologic Research.