Improved algorithms for constructive multi-phase test point insertion for scan based BIST

Abstract

New test point selection algorithms to improve test point insertion quality and performance of a multi-phase test point insertion scheme, while reducing the memory requirement of the analysis are proposed. A new memory efficient probabilistic fault simulation method, which also handles the reconvergences to a limited extent for increased accuracy, is introduced. Synergistic control point insertion is targeted for higher test point insertion quality. Experiments conducted on various large industrial circuits demonstrate the effectiveness of the new algorithms.