Abstract
To ensure continuity in technology scaling, system level technology boosters will need to be introduced to complement Design-Technology Co-Optimization. We illustrate this evolution with the introduction of buried power rails and backside power delivery. These can provide 20% and 30% area scaling benefit respectively. Backside power delivery further improves IR drop providing up to 15% performance enhancement enabling PPAC scaling at system level.
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CITATION STYLE
Ryckaert, J., Gupta, A., Jourdain, A., Chava, B., Van Der Plas, G., Verkest, D., & Beyne, E. (2019). Extending the roadmap beyond 3nm through system scaling boosters: A case study on Buried Power Rail and Backside Power Delivery. In 2019 Electron Devices Technology and Manufacturing Conference, EDTM 2019 (pp. 50–52). Institute of Electrical and Electronics Engineers Inc. https://doi.org/10.1109/EDTM.2019.8731234
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