Two novel low power and very high speed pulse triggered flip-flops

Abstract

Two novel low power and high-speed pulse triggered flip-flops were presented in this paper. Short circuit current was controlled, and race condition between pull-up and pull-down branches was removed, which caused reduction of power consumption. On the other hand, the number of stack transistors in the discharging path was reduced which decreased delay of the flip-flops. The first proposed flip-flop reduced the number of transistors and the second proposed flip-flop used conditional data mapping and removed floating node of the first flip-flop. Post-layout simulation result showed that the first proposed flip-flop reduced 21% of power delay product and the second proposed flip-flop reduced 16% of power delay product in comparison with other flip-flops in 50% of data switching activities.