Architecture and Design of 4x4x4 NOC for Multicore SOC

Abstract

Network on Chip (NoC) architecture provides a good way of realizing efficient Interconnections in multiprocessors. 3D NoC uses a mesh topology with wormhole switching and stall-go flow control scheme. It improves scalability, diminished concurrent communication, and low power consumption. NoC communication is realized by data packets and forwarded among the network which routes according to Look-Ahead-XYZ routing algorithm (LA-XYZ). The proposed paper focuses on design and verification of 4x4x4 3D NoC. The proposed 3D Network on Chip is designed in VHDL language at RTL level and verified on Xilinx using ISE 14.1 tools. The targeted device is FPGA Virtex-6 XC5VLX30.The minimum input arrival time before clock and maximum output time required time after clock is estimated as 13.094 ns and 10.107 ns respectively.