Graded index couplers for next generation chip-to-chip and fiber-to-chip photonic packaging

Abstract

The transition towards designs which co-package electronic and photonic die together in data center switch packages has created a scaling path to Petabyte per second (Pbps) input/output (I/O) in such systems. In a co-packaged design, the scaling of bandwidth, cost, and energy will be governed by the number of optical I/O channels and the data rate per channel. While optical communication provide an opportunity to exploit wavelength division multiplexing to scale data rate, the limited 127 µm pitch of V-groove based single mode fiber arrays and the use of active alignment and bonding for their packaging present challenges to scaling the number of optical channels. Flip-chip optical couplers which allow for low loss, broadband operation and automated passive assembly represent a solution for continued scaling. In this paper, we propose a novel scheme to vertically couple between silicon based waveguides on separate chips using graded index couplers in combination with an evanescent coupler. Simulation results using a 3D finite-difference time-domain solver are presented, demonstrating coupling losses as low as 0.35 dB for a chip-to-chip gap of 11 µm; 1 dB vertical and lateral alignment tolerances of approximately 2.45 µm and ± 2.66 µm, respectively; and a possible 1 dB bandwidth of greater than 1500 nm. These results demonstrate the potential of our coupler as a universal interface in future co-packaged optics systems.