A 14-bit dual-split capacitor array DAC design based successive approximation ADC

Abstract

For the application of Internet-of-Things (IoTs),a low power, medium resolution ADCs are needed for converting the front end analog signal. In this research work presents, a Successive Approximation Register-Analog-to-Digital (SAR-ADC) design with minimum Capacitive Array Digital-to-Analog converter. Here, a novel Dual-Split-Three-Section (DSTS) capacitor array DAC (DSTS-CDAC) has been proposed to perform 14-bit SAR-ADC function while retaining Signal-to-Noise Destruction Ratio (SNDR) of 69.7dB for the ADC. The use of monotonic switching scheme exhibited reduced capacitive array power consumption for 14-bits CDAC. Furthermore, it requires 185 times unit capacitances on contrary to the conventional SAR-ADC designs, which requires 256 times unit capacitances in a capacitive array. A significant reduction of 28% area too applauds proposed design for low cost CMOS development. Also, in this paper, the linearity performances are theoretically analysed and behavioural simulations are performed. These values are comparable to the conventional method and found to be improved. This design uses 1.5V supply and 100kSps sampling frequency. Moreover, the design is made fully differential, thereby reducing the noise parameter to a considerable extent.