Improved fault tolerant ALU architecture

Abstract

The birth to IC technology by Moore became driving force behind civilization and it spent almost 45 years successfully without any scruple in mind. It affected life of a mankind and brought pivotal moment in civilization. Now technology is hitting atomic levels and soon limits will be touched. Therefore time has come to rethink for an alternative solution that may slow down exponential rate demonstrated by Moore. Reversible computing is emerging as a superior technology and soon will be future of all smart computing applications. Although renowned physicists and computer scientists have investigated remarkable results in reversible logic based arithmetic logic unit (ALU) designing still research in the field of reversible ALU with add on fault tolerance is under progress and there is scope of further optimization. This paper aims in investigation of improved fault tolerant ALU architecture using parity preserving fault tolerant reversible adder (FTRA), double Feynman and conservative Fredkin gates. Performance evaluation of proposed architecture is done in respect of functionality, garbage lines, ancillary lines, quantum cost and number of gates. The quantum cost of all gates is verified using RCViewer+ tool. The proposed architecture is coded in Verilog HDL, Synthesized and simulated using EDA (Electronic Design Automation) tool-Xilinx ISE design suit 14.2.