Abstract
In this paper, a floating-point multiplier with high speed and area efficient is presented. The multiplier is designed, optimized, and implemented on an FPGA based system. A comparison between the results of the proposed design and a previously reported one is provided. The effect of rounding on the area, speed, and accuracy for three different configurations is examined.
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CITATION STYLE
Aty, G. H. A., Hussein, A. I., Ashour, I. S., & Mones, M. (2003). High-speed, area-efficient FPGA-based floating-point multiplier. In Proceedings of the International Conference on Microelectronics, ICM (Vol. 2003-January, pp. 274–277). Institute of Electrical and Electronics Engineers Inc. https://doi.org/10.1109/ICM.2003.237828
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