Abstract
Adaptive routing has been proposed as a means of improving performance and fault-tolerance in multicomputer networks. While a number of algorithms have been proposed, few adaptive routers have been implemented in hardware. This paper presents the design and implementation of Ariadne - a prototype single chip, hardware router. The primary motivation is tolerance to link and router failures, while reconciling conflicting demands on performance. This is achieved by implementing the m-misroute backtracking protocol (MB-m) using the pipelined circuit-switching (PCS) communication mechanism. Ariadne implements two virtual data channels and one virtual control channel per physical link. The router is self-timed with single flit buffering at the input and output ports, and is fully adaptive.
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CITATION STYLE
Allen, J. D., Gaughan, P. T., Schimmel, D. E., & Yalamanchili, S. (1994). Ariadne - an adaptive router for fault-tolerant multicomputers. In Conference Proceedings - Annual International Symposium on Computer Architecture, ISCA (pp. 278–288). Publ by IEEE. https://doi.org/10.1145/192007.192040
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