A Modified Fused Floating Point Three Term Adder

Abstract

This paper is about a modified architecture for a fused floating point three term adder. The important feature of a fused floating-point three-term adder is its ability to do multiple additions in same block to get better performance as well as accuracy compared to a conventional discrete floating point adder. The parallel prefix adder is one amongst the fastest adders and out of which the han-carlson adder represents a blend of the kogge-stone adders and brent-kung adder. In this work, han carlson adder is used to enhance the performance of the three term adder along with various optimization techniques. The adder is implemented using Verilog language in Xilinx ISE Design suite 14.2 and all Simulations are carried out in Isim simulator. Synthesis is done using Cadencetool.