Design for stuck-at fault testability in multiple controlled toffoli-based reversible circuits

Abstract

Testability leads to a large increment in operating costs from their original circuits which drastically increases the power consumption in logic circuits. A new design for testability methodology for the detection of stuck-at faults in multiple controlled Toffoli based reversible circuits is presented. The circuit is modifed in such a manner that the applied test vector reaches all the levels without any change in values on the wires of the circuit. A (n+1) dimensional general test set containing only two test vectors is presented, which provide full coverage of single and multiple stuck-at faults in the circuit. The work is further extended to locate the occurrence of stuck-at faults in the circuit. Deterministic approaches are described and the modifcation methodology is experimented on a set of benchmarks. The present work achieved a reduction up to 50.58 per cent in operating costs as compared to the existing work implemented on the same platform.