Towards On-Chip Learning for Low Latency Reasoning with End-to-End Synthesis

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Abstract

The Software Defined Architectures (SODA) Synthesizer is an open-source compiler-based tool able to automatically generate domain-specialized systems targeting Application-Specific Integrated Circuits (ASICs) or Field Programmable Gate Arrays (FPGAs) starting from high-level programming. SODA is composed of a frontend, SODA-OPT, which leverages the multilevel intermediate representation (MLIR) framework to interface with productive programming tools (e.g., machine learning frameworks), identify kernels suitable for acceleration, and perform high-level optimizations, and of a state-of-the-art high-level synthesis backend, Bambu from the PandA framework, to generate custom accelerators. One specific application of the SODA Synthesizer is the generation of accelerators to enable ultra-low latency inference and control on autonomous systems for scientific discovery (e.g., electron microscopes, sensors in particle accelerators, etc.). This paper provides an overview of the flow in the context of the generation of accelerators for edge processing to be integrated in transmission electron microscopy (TEM) devices, focusing on use cases from precision material synthesis. We show the tool in action with an example of design space exploration for inference on reconfigurable devices with a conventional deep neural network model (LeNet). Finally, we discuss the research directions and opportunities enabled by SODA in the area of autonomous control for scientific experimental workflows.

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Castellana, V. G., Agostini, N. B., Limaye, A., Amatya, V., Minutoli, M., Manzano, J., … Ferrandi, F. (2023). Towards On-Chip Learning for Low Latency Reasoning with End-to-End Synthesis. In Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC (pp. 632–638). Institute of Electrical and Electronics Engineers Inc. https://doi.org/10.1145/3566097.3568360

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