Efficient replica bitline technique for variation-tolerant timing generation scheme of SRAM sense amplifiers

Abstract

An efficient replica bitline (RBL) technique for reducing the variation of sense amplifier enable (SAE) timing is proposed. Both RBLs and four-fold replica cells compared with the conventional RBL technique are utilised to favour the desired operations. Simulation results show that the standard deviation of SAE can be suppressed by 44.25% and the cycle time is also reduced by ∼30% at a 0.8 V supply voltage in TSMC 65 nm technology. Additionally, the area of the proposed scheme is nearly the same as that of the conventional RBL scheme.