A leakage power aware transmission gate level shifter

Abstract

The clustered voltage scaling systems are ultimate power reduction techniques, uses voltage level shifters (LSs) to interface multi voltage domains to reduce power at system level. The LS may become overhead when its own power consumption and delay is high. In this paper we presented a new schematic of level shifter with single supply voltage to perform voltage level shift, which uses Transmission gate based circuit topology. The simulation results says it has energy per transition is 1.80E-14 J at 1 MHz frequency and the level shifter delay is 2.6 ns at VDDL 0.3V and VDDH 1V. The design has simulated by using 90nm CMOS technology files. This new architecture is more efficient then existing architectures.