FPGA implementation of r-FIFO-based high-speed data acquisition IOT architecture model

Abstract

To enhance the utilization efficiency of Internet of Things (IoT) and cyber-physical system technologies, more collaboration in data transmission is recommended. These applications receive data from multiple sensors; hence, addition of efficient data acquisition system becomes mandatory. Past research works report use of data sharing among the tasks; however, this is only possible as long as the data meets the time-sensitive requirements of the tasks. To have an efficient communication between the different nodes of the IoT applications, this research work proposes use of reconfigurable first-in, first-out (r-FIFO) design to acquire data. This would not only reduce total sensing time but also the energy consumption, which is a conspicuous concernment in IoT systems for the offline scenarios. This paper first provides an optimal algorithm for FIFO tasks in the offline case, and later the r-FIFO architecture is synthesized on the FPGA board using ZYBO (zynq- 7000). Further, the design is being implemented in SCL 180 nm CMOS ASIC technology. Performance measurement is performed by evaluating the frequency, total power, and the energy per bit of the design.