Performance evaluation and design trade-offs for network-on-chip interconnect architectures

Abstract

Multiprocessor system-on-chip (MP-Sack) platforms are emerging as an important trend for Sack design. Power and wire design constraints are forcing the adoption of new design methodologies for system-on-chip (Sack), namely, those that incorporate modularity and explicit parallelism. To enable these MP-Sack platforms, researchers have recently pursued scaleable communicationcentric interconnect fabrics, such as networks-on-chip (NOTCH), which possess many features that are particularly attractive for these. These communication-centric interconnect fabrics are characterized by different trade-offs with regard to latency, throughput, energy dissipation, and silicon area requirements. In this paper, we develop a consistent and meaningful evaluation methodology to compare the performance and characteristics of a variety of NoC architectures. We also explore design trade-offs that characterize the NoC approach and obtain comparative results for a number of common NoC topologies. To the best of our knowledge, this is the first effort in characterizing different NoC architectures with respect to their performance and design trade-offs. To further illustrate our evaluation methodology, we map a typical multiprocessing platform to different NoC interconnect architectures and show how the system performance is affected by these design trade-offs. © 2005 IEEE.