BlendCache: An Energy and Area Efficient Racetrack Last-Level-Cache Architecture

Abstract

Racetrack memory (RTM) is a promising nonvolatile memory that provides multibit storage cells achieving a higher area and leakage energy efficiency compared to contemporary volatile and nonvolatile memories. These features make RTM a potential candidate to be used as a last-level-cache (LLC). One drawback of the multibit RTM cell is the serialized access to the stored data, resulting in a shift penalty to access a particular bit within the cell. This overhead is particularly critical for LLC tags, for which prior RTM designs place tags either in SRAM or in single-bit RTM cells. While this avoids shifting, these designs require a large number of leaky cells incurring high energy consumption. To address this problem, this article proposes an energy-efficient RTM design called BlendCache that efficiently stores the tags in the leakage-optimized multibit RTM cells. To reduce the RTM shift penalty of these cells, BlendCache exploits the spatial locality of programs by maximizing accesses to nearby locations in RTM. Employing 32-bit RTM cells for a single core, BlendCache reduces the energy consumption by 20.8% and area by 15.2% compared to the state-of-the-art while its impact on performance is negligible. For a 4-core system, the energy improvement translates to 35.9% with 3% performance degradation.