Review of wafer-level three-dimensional integration (3DI) using bumpless interconnects for tera-scale generation

Abstract

The prospects of three-dimensional (3D) integration for Terabyte large scale integration using bumpless interconnects with low-aspect-ratio TSVs and ultra-thinning are discussed. Bumpless (no bump) interconnects between wafers are a second-generation alternative to the use of microbumps for Wafer-on-Wafer (WOW) technology. Ultra-thinning of wafers down to 4 μm provides the advantage of a small form factor, not only in terms of the total volume of 3D ICs, but also the aspect ratio of Through- Silicon-Vias (TSVs). Our bumpless interconnects technology is classified into Via-Last, which is performed from the front side after thinning, and stacking Back-to-Front, in which any number of thinned 300mm wafers and/or heterogeneous dies can be integrated. From an economic point of view, in many situations WOW is the leading 3D process because stacking at the wafer level drastically increases the processing throughput, and using multi-level bumpless interconnects, with individual wiring die-to-die, provides an appropriate yield that is equivalent to or greater than that achievable with 2D processes when scaling down to 22 nm nodes and beyond.