HLS-compiled PYNQ-based cardiac arrhythmia detection system leveraging quantized ECG beat images

Abstract

Electrocardiogram (ECG) analysis is a widely used non-invasive method for detecting cardiac disorders. Efficient hardware inference of deep learning (DL) models for accurate diagnostics is an emerging focus in biomedical applications. However, deployment of computationally intense DL architecture on resource constrained field-programmable gate array (FPGA) platform is always a challenge. It involves frequent memory access and data reuse, which leads to latency and throughput degradation. This work addresses a portable FPGA based healthcare system for arrhythmia classification. A hardware-aware dual-branch convolutional neural network (CNN) architecture is proposed to enhance FPGA's inherent parallelism, and minimize data-reuse complexity. The hardware modeling of CNN architecture is developed in high-level synthesis (HLS) environment with 4-bit quantized ECG beat images as input. In addition, hardware level optimization techniques are proposed through three key designs: (i) parallel-quantized-pixel wise (PQP) convolution module, (ii) function-merging add-pool unit, and (iii) skip-zero-weight (SZW) architecture. The design removes ReLU activation in convolution and fully connected layers by leveraging unsigned 4-bit integer (UINT4) computations, ensuring non-negative intermediate results. The implemented design utilizes 31.93% of look-up tables (LUTs), 17.75% of flip-flops (FFs), 50.45% of digital signal processing (DSP) units, and 30% of block random-access memory (BRAM) on PYNQ-Z2 FPGA board, and achieves a latency of 236 ms and a throughput of 63 giga operations per second (GOPS) verified using Vivado 2022.2. The proposed system is evaluated on the MIT-BIH Arrhythmia Dataset following the AAMI EC57 standard and achieves 97.79% classification accuracy for five types of ECG beats, demonstrating its real-time potential.