Artificial neural network engine: Parallel and parameterized architecture implemented in FPGA

Milene Barbosa Carvalho; Alexandre Marques Amaral; Luiz Eduardo Da Silva Ramos; Carlos Augusto Paiva Da Silva Martins; Petr Ekel

Conference ProceedingsOPEN ACCESS

Artificial neural network engine: Parallel and parameterized architecture implemented in FPGA

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) (2005) 3776 LNCS 294-299

DOI: 10.1007/11590316_42

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Abstract

In this paper we present and analyze an artificial neural network hardware engine, its architecture and implementation. The engine was designed to solve performance problems of the serial software implementations. It is based on a hierarchical parallel and parameterized architecture. Taking into account verification results, we conclude that this engine improves the computational performance, producing speedups from 52.3 to 204.5 and its architectural parameterization provides more flexibility. © Springer-Verlag Berlin Heidelberg 2005.

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Carvalho, M. B., Amaral, A. M., Da Silva Ramos, L. E., Da Silva Martins, C. A. P., & Ekel, P. (2005). Artificial neural network engine: Parallel and parameterized architecture implemented in FPGA. In Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) (Vol. 3776 LNCS, pp. 294–299). Springer Verlag. https://doi.org/10.1007/11590316_42

Artificial neural network engine: Parallel and parameterized architecture implemented in FPGA

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