Design of system-on-a-chip test access architectures under place-and-route and power constraints

Abstract

Test access is a difficult problem encountered in the testing of core-based system-on-a-chip (SOC) designs. Since embedded cores in an SOC are not directly accessible via chip inputs and outputs, special access mechanisms are required to test them at the system level. We propose test access architectures based on integer linear programming (ILP) that incorporate place-and-route constraints arising from the functional interconnections between cores, as well as system-level constraints on power consumption. As a case study, we apply the ILP models to two representative SOCs, and solve them using a public-domain ILP software package.