FPGA implementation of adaptive multiplier-based linear image interpolation

Abstract

This work provides an image interpolation for multimedia applications by utilizing an adaptive multiplier-based stepwise linear interpolation with clam filter. Image interpolation is also termed as image up-scaling. Generally, while enlarging an image some vacant bit positions are introduced and due to this empty pixel positions, the quality of the image is decreased. Therefore to maintain the quality of the image, new pixels are introduced and those pixels are used to fill the vacant bit positions by using interpolation techniques. In the adaptive interpolation techniques, edge pixels are identified and filtered at prior to the interpolation process. This will improve the quality of the interpolated image. However, the adaptive interpolation scheme increases the complexity of the system. To reduce the complexity, this work uses low complexity stepwise linear interpolation and to maintain the quality it uses multiplier-based linear stepwise (MBLSI) and edge enhancement technique. The experimental results demonstrate that the complexity of the proposed work is less as compared with other related work as well as the quality is also maintained. The proposed work utilizes 275 LUTs to provide the average peak signal to noise ratio (PSNR) of 20.44 dB and structural similarity index (SSIM) as 0.8250. This proposed work increases the PSNR by 0.89 dB from the conventional multiplier-based stepwise linear interpolation. Further the proposed interpolation algorithm utilizes less number of resources in field programmable gate array (FPGA) by comparing with other related interpolation techniques.