Analytical modeling of adiabatic logic with the effects and analysis of performance parameter variations

Abstract

Adiabatic or energy recovery circuits are based on recycling the energy stored in nodal capacitances. For a given amount of energy stored in nodal capacitance, the energy drawn from the source depends on the rate of drawing the charge from the source. Power drawn from the source will be lower if the rate of charging is lower. The efficiency of charging of adiabatic circuits depends on how slowly the capacitance is being charged. We have presented one analytical model of adiabatic logic circuit and find out the expressions for power dissipations in charging and discharging phases. From the expression conclusions on design parameters are made. We have also examined the power dissipation of the adiabatic circuits with the variation of some device parameters like width of the transistors, load capacitance, power clock frequency and input data frequency.