An alternative radiation hardened by layout design in a CMOS technology

Abstract

Electronic circuits used in aerospace industry, particle physics research, and medical equipment need to work in radioactive environments and long-term exposure to radiation causes degradation of their electrical properties. One of the causes of device degradation is the effect of the total ionizing dose (TID). The accumulation of positive charges in silicon oxide (SiO2) is the main problem that generates the TID, the accumulation of charges causes changes in the threshold voltage, leakage current and the generation of parasitic transistors between N-type regions. To reduce the degradation caused by TID, several techniques have been researched, one of which is radiation hardening by design (RHBD). This paper presents a new layout technique named hourglass transistor; this new layout improves the radiation response to TID. The behavior of devices with the new layout was analyzed using 3D simulations with physical models, and a 130nm CMOS technology.