VLSI design of an area & time efficient design of overloaded CDMA architecture using han carlson adder

Abstract

On-chip interconnects are the performance bottleneck in modern system-on-chips. Code-division multiple accesses (CDMA) have been proposed to implement on-chip crossbars due to its fixed latency, reduced arbitration overhead, and higher bandwidth. In this paper, we advance overloaded CDMA interconnect (OCI) to enhance the capacity of CDMA network-on-chip (NoC) crossbars by increasing the number of usable spreading codes. Serial-OCI and P-OCI architecture variants are presented to adhere to different area, delay, and power requirements. Compared with the conventional CDMA crossbar, on a Xilinx Spartan-3E FPGA kit, the serial OCI crossbar achieves 100% higher bandwidth, 31% less resource utilization, and 45% power saving, while the parallel OCI crossbar achieves N times higher bandwidth compared with the serial OCI crossbar at the expense of increased area and power consumption. Further to increase the speed of OCI crossbar we are implementing Han Carlson adder in place of parallel adder architecture The use of Han-Carlson adder gives better performance than the existing system by 38% area reduced and 49% speed increased.