The Reduceron reconfigured and re-evaluated

Abstract

A new version of a special-purpose processor for running lazy functional programs is presented. This processor - the Reduceron - exploits parallel memories and dynamic analyses to increase evaluation speed, and is implemented using reconfigurable hardware. Compared to a more conventional functional language implementation targeting a standard RISC processor running on the same reconfigurable hardware, the Reduceron offers a significant improvement in run-time performance. © Copyright Cambridge University Press 2012.